An embodiment of the present disclosure generally relates to virtual platform simulations, and specifically relates to sliding time window control mechanism for parallel execution of multiple processor core models in a virtual platform simulation.
Most virtual platform simulations, such as SystemC based simulations, are inherently sequential in nature. Many hardware platforms are somewhat parallel or becoming increasingly parallel, which reduces simulation performance using SystemC. This is particularly true for symmetric multiprocessing (SMP) platforms; i.e., platforms in which a number of tightly coupled processor cores execute concurrently. SystemC based simulations of SMP platforms cannot easily be parallelized. Many hardware models are not configured as thread-safe or re-entrant because, in an inherent sequential SystemC simulation, thread-safety is not required and would have a negative impact on simulation performance. A hardware model is a thread-safe model if operations of the hardware model are executed in an operating system (OS) thread simultaneously with execution of operations of other instances of the same or different hardware models in other OS threads without unintended interactions between the concurrent threads.
Operations that manipulate a state that is local to a thread will usually be thread-safe, whereas operations that make concurrent updates to state that is shared between threads will usually not be thread-safe. Making such operations thread-safe will usually require the use of OS synchronization mechanism to achieve mutually exclusive access to the shared state, or the use of so-called atomic operations that the hardware provides for the thread-safe manipulation of shared state. A hardware model is a re-entrant model if an OS thread executing operations of the hardware model can be interrupted, and then be called again (“re-entered”) to correctly resume the execution of remaining operations. Many legacy hardware models cannot easily be modified to be configured as thread safe or re-entrant. Parallelizing of a SystemC kernel also requires significant engineering effort, because the kernel has been implemented and optimized strictly for the sequential use case.
Conventional processor core models use temporal decoupling to increase simulation performance. A processor core model within a virtual platform simulation can be allowed to execute operations ahead of a global simulation time for a limited period of time. If a processor core model is to interact with one or more elements (hardware models) in a rest of the virtual platform simulation outside of the processor core model, the processor core model can synchronize to allow the rest of the virtual platform simulation to catch up with the execution of the processor core model. Two processor core models that utilize this form of temporal decoupling are conventionally executed in sequence.
Various conventional mechanisms can be applied to set a maximum quantum of time for which a processor core model is allowed to execute operations ahead of a rest of a virtual platform simulation outside of the processor core model. For example, the SystemC/Transaction Level Modeling 2.0 (TLM2.0) standard describes a temporal decoupling mechanism with a static quantum of time. In an implementation of a SystemC reference simulator, quanta start at equidistant time steps of a global simulation time. Each quantum of time allows a processor core model to execute operations ahead of the rest of the virtual platform simulation for a fixed number of clock cycles.
In another conventional mechanism, a size of a quantum is calculated dynamically in a manner to interrupt an execution of a processor core model at time instances where changes in a global simulation state are expected, wherein the changes in the global simulation state should be observed by the processor core model as soon as the changes occur. This implementation takes a current status of the SystemC scheduler into account. Specifically, simulation events that are already scheduled with the SystemC kernel can be used to obtain an upper bound for a next quantum of the processor core model. This ensures that the processor core model does not run past that event, which, for example, can be an interrupt request to which the processor core model should be able to react quickly.